To electrically test a circuit board, a testing machine of a type well known in the art launches one or more test signals into the board through a test fixture and then recovers, via the fixture, the signal(s) generated in response to the test signals. Present day test fixtures for coupling a circuit board under test to a testing machine typically comprise two sets of electrically conductive pins or nails. The pins of the first set are arranged so each contacts a separate node on the circuit board while the pins of the second set are arranged so each contacts a separate one of a set of uniformly spaced contacts on the testing machine. Typically, the nodes on the circuit board are not uniformly spaced like the contacts on the testing machine so that some, if not all, of the pins of the first set are offset from the pins of the second set. In some instances the pins of the second set may be replaced by flexible metal connectors.
In a conventional test fixture, each pin of the first set is electrically coupled to a separate pin of the second set by a length of wire. Fixtures of this type, referred to as "wired fixtures", tend to incur poor performance at high frequencies (&gt;10 MHz.) due to cross talk. Improved fixture performance can be obtained by utilizing a printed circuit board, referred to as a "translator board," rather than individual wires, to interconnect the pins of the first set to those of the second set. A typical translator board consists of two outer layers of insulative material (e.g., FR-4), in between which are sandwiched two inner layers of insulative material, each having conductive metallized paths thereon.
On the exposed surface of a first one of the outer layers are a set of metallized areas, hereinafter referred to as "test points" which are arranged to contact a separate one of the first set of pins. The exposed surface of the other outer layer is provided with a set of metallized areas, hereinafter referred to as "grid points," arranged to contact each of the second set of pins. Each test point is connected to an appropriate one of the grid points through the combination of a longitudinal and a latitudinal metallized path, each running orthogonal to the other on a major surface of a separate one of the pair inner layers of the translator board. The test points and grid points are each connected to a separate one of the longitudinal and latitudinal paths, respectively, by a separate one of a plurality of metal-plated vias. Each longitudinal path is linked to a latitudinal path by a metal-plated via as well.
The most difficult task in fabricating "translator board" type test fixtures is routing the translator board, that is, determining the geometry (i.e., the length and the locations) of the longitudinal and latitudinal paths so each test point is connected to an appropriate grid point. The length and location of each longitudinal and latitudinal path is dependent on the assignments (i.e., the pairings) of the test points and grid points. Once each test point has been assigned to an appropriate one of the grid points, the longitudinal and latitudinal paths can easily be routed on a separate one of the inner layers using a conventional channel routing program as is known in the art.
Assigning the test points to the grid points is not a trival task. In order to achieve good fixture performance at high frequencies, the composite path between each test point and grid point should be kept short. To this end, it is desirable for each test point to be assigned to the closest grid point. However, the grid point closest to the test point may not be connected to an appropriate contact on the testing machine. For example, the contact on the testing machine associated with the grid point closest to the test point may not be of the appropriate logic family for the node on the circuit board associated with the test point.
At the present time, assignment of the test points to the grid points is done on an ad hoc basis. As a consequence, there is no assurance that each test point is necessarily assigned to the closest appropriate grid point.
Thus, there is a need for an technique for assigning each of a plurality of test points on a substrate to an appropriate one of a set of grid point such that each test point is automatically assigned to the closest one of the grid points appropriate for the test point.